The present invention relates, in general, to heterojunction field effect transistors, and more particularly, to heterojunction field effect transistors having a superlattice buffer layer underneath a channel layer.
Field effect transistors operate by controlling current flow through a channel region with a gate electrode. To maintain current control it is necessary to confine charge carriers within the channel region. In metal oxide semiconductor FET (MOSFET) technology current confinement is accomplished by separating the channel region from the gate electrode by an insulating oxide region. In heterojunction FET (HFET) technology, however, the insulating region is not used and carrier confinement is achieved by a heterojunction barrier layer between the gate electrode and the channel region. In other words, the channel is formed by a quantum well using a material with a narrower bandgap than the barrier layer. A similar heterobarrier may be used below the channel region to keep charge carriers from straying into the substrate or buffer layer on which the channel region is formed. In HFET devices, the ability to confine charge carriers within the channel region is of great importance and directly affects device parameters such as pinch-off voltage and gate leakage.
The degree of confinement is determined by a difference in energy between a ground state in the channel region and a ground state of an adjacent layer. Typically, a gallium arsenide (GaAs) buffer layer underneath the channel region provided a gradual energy difference arising from the difference in doping levels of the channel and buffer layer, and thus poor charge confinement. Even when indium gallium arsenide (InGaAs) is used for the channel region, the difference in energy between the back side of the channel and the GaAs buffer is only about 0.1 eV. To compensate for this low energy difference, channel regions had to be made quite thick. Thick channel regions lower the ground state energy in the channel region improving confinement at the expense of increased epitaxial growth time and lower charge carrier concentration and transconductance. Further improvement is desirable.
The barrier used below the channel region serves two primary functions. In addition to confining carriers within the channel region, the barrier is also a mechanical buffer between a semi-insulating substrate and the channel region. The substrate usually has a high defect density, and the buffer layer functions, at least in part, to prevent substrate defects from propagating upwards to the channel region. Recently, superlattice structures have been used to replace a portion of the thick GaAs buffer layer. Superlattice structures stop defect propagation better than single material layers of comparable thickness. The superlattice structure was relied on for its mechanical properties and little attention was directed towards using solid state electronic properties of the superlattice. Even when superlattice layers were used, however, thick GaAs buffer layers were formed between the superlattice and the channel layer. Until now, the superlattice structure was separated from the channel by a GaAs buffer so the solid state properties were believed to be unimportant.
To conduct current through the channel region, charge carriers, holes for a P-channel device and electrons for an N-channel device must be provided in the channel region. Higher charge carrier concentration in the channel region results in higher transconductance and lower channel resistance in the HFET device. HFETs are usually modulation doped by placing a thin, heavily doped layer called a carrier supply layer in the barrier layer so that excess charge carriers tunnel from the carrier supply layer through, or thermionically transported over the top of the barrier layer to the quantum well channel region. Charge carriers are then trapped in the quantum well.
When the substrate is biased, a gradual energy gradient is produced in the conduction band of a GaAs buffer layer. This gradual slope in the conduction band provided a continuum of states in which energetic charge carriers in the channel could escape the channel by moving into the buffer layer. As the charge carriers gained more energy, they escaped as far as possible into the buffer layer. Of course, the farther into the buffer layer the charge carriers penetrated, the less control could be exercised on them by the gate electrode. To enhance carrier confinement and improve gate control, it is desirable to have a large energy discontinuity rather than a gradual slope in the conduction band.
Accordingly, it is an object of the present invention to provide a heterojunction field effect transistor having improved transconductance.
A further object of the present invention is to provide a heterojunction field effect transistor having a comparatively thin superlattice layers formed directly underneath the channel region.
A further object of the present invention is to provide a heterojunction field effect transistor having a quantized energy gradient between the channel region and an underlying substrate.
Another object of the present invention is to provide an HFET device having improved pinch off voltage.
Still another object of the present invention is to provide an HFET structure with a short epitaxial growth time.
A further object of the present invention is to provide an HFET device having improved charge carrier confinement within the channel region.